1. Field of the Invention
The present invention relates to a field effect transistor (FET) and more particularly to a heterojunction FET.
2. Description of the Related Art
A heterojunction FET of which a HEMT (High Electron Mobility Transistor) with a GaAs-based or InP-based group III-V compound semiconductor is typical has been being employed as a low-noise high-output high-efficiency high-frequency device for various purposes. FIG. 61 is, for example, a cross-sectional view of the structure of a FET shown in Japanese Patent Application Laid-open No. 64924/1998. In FIG. 61, referential numeral 1005 indicates a semi-insulating GaAs substrate; 1004, a buffer layer formed on the semi-insulating GaAs substrate 1005; 1003, an n-GaAs active layer formed in a prescribed region of the buffer layer 1004; 1007, an n+ ohmic contact region formed in a region of the buffer layer 1004 where no n-GaAs active layer 1003 is formed; 1002, an n-AlGaAs etching stopper layer formed on the n-GaAs active layer 1003; 1001, an i-GaAs layer formed in a prescribed region of the n-AlGaAs etching stopper layer 1002; 1008, an SiO2 insulating film formed on the i-GaAs layer 1001; 1015 and 1016, source/drain electrodes made of AuGe-based metal, being formed on the n+ ohmic contact region 1007; and 1017, a gate layer made of a p+-type semiconductor. Such a FET having a p-n junction in a gate region as described above is known as a JFET (Junction Field Effect Transistor). Therein, the p-n junction is biased and the drain current is controlled through the adjustment of the width of the space charge region directly under the gate.
Next, referring to FIGS. 62-64, a method of manufacturing the afore-mentioned semiconductor device is described. In the first step thereof, layers 1001-1005 are formed by the epitaxial crystal growth method, in succession. An n+ ohmic contact region 1007 is then formed in each prescribed region on the i-GaAs layer 1005, using the ion-implantation/annealing method. After that, over the entire surface of the semiconductor substrate, an SiO2 insulating film 1008 is deposited and, using resist masks 1009, an opening is made in the SiO2 film 1008. Further, the i-GaAs layer 1001 is dry etched and thereby a gate region is formed (FIG. 62).
Next, a semiconductor layer 1017 of p+-type conductivity is formed in the gate region by either an MOCVD (Metal Organic Chemical Vapour Deposition) method or a CBE (Chemical Beam Epitaxy) method, using the SiO2 insulating film 1008 as a mask (FIG. 63). After that, using a photoresist 1014 as a mask, openings for source/drain electrode formation sections are made in the SiO2 insulating film 1008 (FIG. 64), and then, using the same photoresist 1014, a drain electrode 1015 and a source electrode 1016 of AuGe-based metal are formed by the deposition/lift-off method, whereby a semiconductor device shown in FIG. 61 is obtained.
The structure of a conventional semiconductor device and the procedure of a manufacturing method thereof are as described above. However, in forming a semiconductor layer of p+-type conductivity, if the formation is made on AlGaAs, the amount of energy discontinuity between the valance bands of AlGaAs and GaAs or those of AlGaAs and InGaAs is small so that, with an applied voltage, holes are made to pour forth, which leads to deterioration of withstand voltage characteristic and unstabilization of operations in the FET.
Further, since Al is easily oxidized to form a thin natural oxidation film, the morphology of the p+-type semiconductor is considerably inferior in quality. Moreover, when a p+-type semiconductor is formed on AlGaAs, numerous interface states turn up on the interface therebetween. Due to these factors, when such a semiconductor device is utilized as a high-frequency device, high frequency characteristic thereof markedly deteriorates.
In addition, because the surface of the AlGaAs layer on which the p+-type semiconductor is grown is formed by dry etching, some damage is produced on the AlGaAs layer. Yet, the selectivity of this dry etching method between these two substances is not particularly good. This brings about deterioration of high-frequency characteristic as well as dispersion of various characteristics of the FET when fabricated.
Electrical resistances that arise in various sections of a FET by way of distributed constants include contact resistances from respective ohmic electrodes to the channel layer and a sheet resistance under the gate. Meanwhile, ON-resistance of a FET is the whole resistance from the source electrode to the drain electrode. As mentioned in IEEE GaAs IC Symposium, pp. 119 (1996), a low ON-resistance is essential to attain a high output and a high efficiency in low-voltage operations. Nevertheless, contact resistances from the ohmic electrodes to the channel layer in conventional structures are notably high.
An object of the present invention is to improve withstand voltage characteristic of a JFET and realize stable operations of a JFET.
Another object of the present invention is to achieve better morphology in forming a semiconductor of p+-type conductivity and suppress substantially creation of the interface states and thereby enhance high frequency characteristic.
A further object of the present invention is to improve a method of manufacturing a semiconductor substance and thereby reduce deterioration of high frequency characteristic as well as dispersion of various characteristics of JFET when fabricated.
A still further object of the present invention is to change the epitaxial structure and thereby lower the contact resistance from the cap layer to the channel layer.
A still further object of the present invention is to achieve a structure over which control can be easily made in forming semiconductor substances.
A still further object of the present invention is to provide a manufacturing method of a FET wherein, in gate formation, structure control is easy and good uniformity is obtainable.
The present invention relates to a field effect transistor having, on a semi-insulating compound semiconductor substrate:
a buffer layer;
an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer;
source/drain electrodes formed on a first conductive-type semiconductor ohmic contact layer which is formed either on said active layer or on a lateral face thereof;
a gate layer made of a second conductive-type epitaxial growth layer; and
a gate electrode formed on said gate layer; which further has:
between said second conductive-type gate layer and said channel layer, a semiconductor layer (referred to as xe2x80x9cenergy discontinuity layerxe2x80x9d, hereinafter) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer.
The present invention provides a field effect transistor; wherein:
(1) said energy discontinuity layer is made of InGaP;
(2) said first conductive-type is n-type and second conductive-type is p-type;
(3) said channel layer is composed of either InGaAs or GaAs and said second conductive-type gate layer is a layer composed of substances selected from the group consisting of GaAs, AlGaAs, InGaAs and InGap.
(4) a semiconductor layer to form a first recess is formed on said energy discontinuity layer and another semiconductor layer to form a second recess which is wider than said first recess is formed on said semiconductor layer to form a first recess, and said second conductive-type gate layer is formed in the first recess;
(5) the ohmic contact layer to provide ohmic contacts for source/drain electrodes is formed on said energy discontinuity layer and said second conductive-type gate layer is formed within a one-stage recess formed with said ohmic contact layer;
(6) while as described in (5), the ohmic contact layer is formed by regrowth on said energy discontinuity layer;
(7) while as described in (5), the ohmic contact layer is consecutively formed, by epitaxial growth, on said energy discontinuity layer made of InGaP, and, using said InGaP layer as an etching stopper layer, said ohmic contact layer is etched by means of wet etching to form a recess, and a second conductive-type gate layer is formed, by regrowth, in said formed recess;
(8) the ohmic contact layer is a layer formed by regrowth after source/drain electrode formation regions of an active layer which, at least, includes a channel layer are removed selectively;
(9) while as described in any one item among (4) to (8), a semiconductor layer or layers within the active layer lying above the channel are a layer or layers essentially consisting of In, Ga and P;
(10) a part or all of said active layer is formed by regrowth together with said second conductive-type gate layer in a depressed section that is formed in the semiconductor layer or layers formed on the buffer layer;
(11) while as described in (10), said semiconductor layer or layers exposed in said formed depressed section are a semiconductor layer containing no Al;
(12) while as described in (10) or (11), said semiconductor layers exposed in said depressed section consist of an etching stopper layer and the ohmic contact layer for source/drain electrodes formed on said stopper layer, and said depressed section is formed in the ohmic contact layer lying over the etching stopper layer;
(13) while as described in (10) or (11), said semiconductor layers exposed in said depressed section consist of the ohmic contact layer for source/drain electrodes and the buffer layer, and, within said formed depressed section, the whole active layer is formed by regrowth;
(14) said second conductive-type gate layer is formed in contact with said energy discontinuity layer; and
(15) while as described in any one item among (4) to (7), either one or both of the ohmic contact layer for source/drain electrodes and the second conductive-type gate layer formed on the active layer are formed on an InGaAsP layer over said energy discontinuity layer.
Further, the present invention relates to a method of manufacturing a field effect transistor as described above and includes the following embodiments.
(a) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a contact layer for source/drain electrodes, by epitaxial growth, in succession;
forming a wide second recess in said contact layer;
forming a first recess in the active layer exposed in this second recess; and
regrowing selectively a gate layer having a second conductive-type conductivity in said first recess; wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and said first recess is formed by means of wet etching, using said InGaP layer as an etching stopper layer;
said energy discontinuity layer is a layer composed of InGaP, and the steps further comprises additional steps of forming an active layer which includes an InGaAsP layer on said InGaP layer and said contact layer on said active layer, and forming the first recess in said active layer which includes said InGaAsP layer by means of wet etching, using said InGaP layer as an etching stopper layer; or
semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(b) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a contact layer for source/drain electrodes, by epitaxial growth, in succession;
forming, at least, a recess in said contact layer; and
regrowing selectively a gate layer having a second conductive-type conductivity in said recess;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and the recess is formed in said contact layer by means of wet etching, using said InGaP layer as an etching stopper layer;
said energy discontinuity layer is a layer composed of InGaP, and the steps further comprises additional steps of forming said contact layer on an InGaAsP layer over said InGaP layer, and forming the recess in said contact layer and the InGaAsP layer by means of wet etching, using said InGaP layer as an etching stopper layer; or
semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(c) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
setting a gate electrode on said gate layer;
removing portions of the gate layer other than the one beneath said gate electrode by means of etching, using the gate electrode as a mask;
removing selectively source and drain regions of said active layer;
regrowing ohmic contact layers for source/drain electrodes in said regions where a portion of the layer is each removed; and
forming source and drain electrodes on said ohmic contact layers, respectively;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and said gate layer is etched by means of wet etching, using said InGaP layer as an etching stopper layer; or
semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(d) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
patterning said gate layer into a prescribed shape;
removing selectively source and drain regions of said active layer;
regrowing ohmic contact layers for source/drain electrodes in said regions where a portion of the layer is each removed;
forming a gate electrode on said gate layer; and
forming source and drain electrodes on said ohmic contact layers, respectively;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and said gate layer is patterned into a prescribed shape by means of wet etching, using said InGaP layer as an etching stopper layer.
Said gate electrode can be formed either before source/drain regions of the active layer are selectively removed, or after ohmic contact layers for source/drain electrodes are formed. Semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(e) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
setting a gate electrode on said gate layer;
removing portions of the gate layer other than the one beneath said gate electrode by means of etching, using the gate electrode as a mask;
regrowing ohmic contact layers for source/drain electrodes in source and drain regions of said active layer; and
forming source and drain electrodes on said ohmic contact layers, respectively;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and said gate layer is etched by means of wet etching, using said InGaP layer as an etching stopper layer;
said energy discontinuity layer is a layer composed of InGaP, and said second conductive-type gate layer is formed on an InGaAsP layer over said InGaP layer, and then, using said InGaAsP layer as an etching stopper layer, said gate layer is patterned into a prescribed shape by means of wet etching; or
semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(f) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an active layer that includes a channel layer and a gate layer with second conductive-type conductivity, in succession;
patterning said gate layer into a prescribed shape;
regrowing ohmic contact layers for source/drain electrodes in source and drain regions of said active layer;
forming a gate electrode on said gate layer; and
forming source and drain electrodes on said ohmic contact layers, respectively;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP, and said gate layer is patterned into a prescribed shape by means of wet etching, using said InGaP layer as an etching stopper layer; or
said energy discontinuity layer is a layer composed of InGaP, and said second conductive-type gate layer is formed on an InGaAsP layer over said InGaP layer, and then, using said InGaAsP layer as an etching stopper layer, said gate layer is patterned into a prescribed shape by means of wet etching.
Said gate electrode can be formed either before ohmic contact layers for source/drain electrodes are formed or after ohmic contact layers for source/drain electrodes are formed. Semiconductor layers comprised in the active layer lying above the channel layer are formed solely with layers whose constituents comprise In, Ga and P.
(g) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, a channel layer, an etching stopper layer to overlie said channel layer and an ohmic contact layer for source/drain electrodes to overlie said stopper layer, by epitaxial growth, in succession;
forming, on said ohmic contact layer, a mask layer in which an opening for a gate region is made;
removing a portion of the ohmic contact layer that is exposed in the opening section of said mask layer so as to form a depressed section; and
forming, in said formed depressed section, a first conductive-type semiconductor layer and a second conductive-type gate layer by epitaxial growth;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP.
Following the semi-conductor layer that rapidly lowers the energy of the valance band, said second conductive-type gate layer can be consecutively formed by regrowth.
(h) A method of manufacturing a field effect transistor which comprises the steps of:
forming, on a semi-insulating compound semiconductor substrate, a first conductive-type buffer layer, an etching stopper layer and an ohmic contact layer for source/drain electrodes to overlie said stopper layer, by epitaxial growth, in succession;
forming, on said ohmic contact layer, a mask layer in which an opening for a gate region is made;
removing a portion of the ohmic contact layer that is exposed in the opening section of said mask layer so as to form a depressed section; and
forming, in said formed depressed section, a first conductive-type semiconductor layer that includes a channel layer and a second conductive-type gate layer by epitaxial growth;
wherein a semiconductor layer (an energy discontinuity layer) that rapidly lowers the energy of the valance band spreading from the gate layer to the channel layer is set between said gate layer and said channel layer.
The method preferably contains the following embodiments:
said energy discontinuity layer is a layer composed of InGaP.
Following the semi-conductor layer that rapidly lowers the energy of the valance band, said second conductive-type gate layer can be consecutively formed by regrowth.
(i) A method of manufacturing a field effect transistor as described in any one item among (a) to (h), wherein said first conductive-type is n-type and second conductive-type is p-type.
(j) A method of manufacturing a field effect transistor as described in any one item among (a) to (i), wherein said channel layer is composed of either InGaAs or GaAs and said second conductive-type gate layer is a layer composed of substances selected from the group consisting of GaAs, AlGaAs, InGaAs and InGaP.
The present invention can improve withstand voltage characteristic of a JFET and realize stable operations of a JFET. This results from a fact that the insertion of an energy discontinuity layer between a gate layer and a channel layer rapidly lowers the energy of the valance band spreading from the gate layer to the channel so that it becomes more difficult for holes to reach the channel when the gate voltage is applied and, thus, avalanche breakdown becomes less likely to occur.
Further, the present invention can achieve better morphology when a semiconductor layer of p+-type conductivity or an ohmic contact layer for source/drain electrodes is formed by regrowth and can suppress creation of the interface states substantially and thereby enhance high frequency characteristic of the JFET. This can be explained as follows. Because formation of a gate layer by regrowth is carried out on a layer such as an InGaP layer constituting an energy discontinuity layer, an interface of which contains no Al, the formation by regrowth can attain excellent morphology. This can substantially suppress creation of the interface states on the regrowth interface which may be brought about by the presence of impurities such as oxygen.
Further, the present invention can reduce deterioration of high frequency characteristic as well as dispersion of various characteristics of the JFET when fabricated. This results from a fact that when the regrowth interface is exposed b wet etching, using the InGaP layer as an etching stopper layer, the etching damage decreases considerably.
The present invention can lower the contact resistance from the cap layer to the channel layer. The explanation lies in a fact that by forming an InGaAsP layer on an energy discontinuity layer, the contact resistance can be reduced by 0.1 xcexa9xc2x7mm or so, compared with the case that no InGaAsP layer is formed. As a result, a high-output high-efficiency FET can be provided.